1. Field of the Invention
The invention relates generally to the field of electronic simulation tools and Electronic Design Automation (EDA). More particularly, the invention relates to a mechanism for increasing runtime performance in a co-/ multi-simulation environment by reducing the number of connections between simulators and/or by reducing traffic between simulators.
2. Description of the Related Art
A number of trends in the design verification market and technological factors are making it increasingly more desirable to be able to employ multiple simulation tools on the same design. For instance, simulation tools are becoming increasingly more specialized while the number of simulation products is steadily growing. Additionally, the simulation task is becoming more decentralized as designers of all types of electronic products are using simulation at every phase of the design process, from analyzing tradeoffs during early architectural analysis, through detailed design of digital and analog circuits to optimize performance and power dissipation, to verification of hardware and firmware for complete system emulation and test. Moreover, design complexity and design diversity are increasing and each design technology (e.g., IC design, board design, and system design) tends to have its own simulation tools, models and vendors. Therefore, a typical design process may incorporate multiple tools from multiple vendors.
Co-simulation, the verification of a design using two simulators concurrently in a simulation session is advantageous to designers in many ways. For example, by employing co-simulation techniques, a designer that is familiar with a particular simulator, such as Verilog-XL, may gain the benefits of additional simulation algorithms, such as Synopsys/EPIC's TimeMill and/or IKOS's NSIM, without leaving the Verilog environment. Additionally, in theory, designers gain the freedom to choose the best verification tools for each task during the design process.
However, existing co-simulation solutions have several shortcomings. By way of example, FIGS. 1A and 1B illustrate simplified examples of design partitions that are mishandled by existing co-simulation technology. In the exemplary partitioned design 100 of FIG. 1A, a first gate 110 has been partitioned to simulator 1 while a second gate 120 and a third gate 130 have been assigned to simulator 2. The output of gate 110 traverses the boundary between simulator 1 and 2, therefore the net 111 associated with the output of gate 110 is labeled as "OUT" in the partition associated with simulator 1. However, net 111 is labeled as "INOUT" in the partition associated with simulator 2 since it is associated with both the input of gate 120 and the output of gate 130. During simulation, when the state of net 111 changes, as a result of the output of gate 110, the simulation environment stops both simulator 1 and simulator 2, synchronizes them in time, transfers information regarding the state change to simulator 2, and then restarts each simulator. Similarly, when the state of net 111 changes, as a result of the output of gate 130, the overhead of starting and stopping simulation must be incurred. Therefore, even though there are no receivers on the boundary net in the partition being simulated by simulator 1, the simulation processing of simulator 1 will unnecessarily be interrupted each time gate 130 causes the state of net 111 to change.
Referring now to FIG. 1B, another example is illustrated in which unnecessary synchronizations occur in the prior art. Design 150 has been partitioned into three partitions: A 160, B 170, and C 180. Partition A 160 includes partition B 170, partition C 180, and a net 191 that is visible in all three partitions 160, 170, and 180. Since the net 191 is coupled to the output of gate 171, the direction associated with the net 191 in partition B 170 is "OUT." The net 191 is coupled to the input of gate 181 in partition C 180; therefore, the direction associated with the net 191 at partition C 180 is "IN." During simulation, when the state of net 191 changes, as a result of the output of gate 171, the simulation environment stops each of the solvers that are simulating partitions coupled by net 191. In this example, therefore, the simulation environment stops the solvers that are simulating partition A 160, B 170, and C 180, synchronizes them in time, transfers information regarding the state change, and then restarts each solver. As in the example of FIG. 1A, even though there are no receivers in partition A 160 for the output of gate 171, prior art simulation processing unnecessary interrupts the solver by which partition A 160 is being simulated.
The unnecessary interruptions caused by the extra connections between partitions, such as those described above, result in an inefficient and more time consuming simulation of a partitioned design. Additionally, the retention of unnecessary connections between simulators by prior co-simulation solutions, wastes memory resources and results in diminished capacity for simulating more complex designs.
In light of the foregoing, what is needed is a simulation solution that reduces the occurrence of simulator synchronizations by eliminating unnecessary connections between simulators.